The present invention relates to a data processing method typified by a circuit simulating method and a simulation program. For example, the invention relates to a technology effectively applied to a simulator used for development or design of semiconductor integrated circuits.
The circuit simulation technology is used as a circuit verification technology for the circuit design and the layout design of a semiconductor integrated circuit. Recently, devices have become smaller and consequently circuits have become large in scale and highly integrated. It becomes obvious that the circuit simulation time becomes long and the amount of data for saving simulation results increases. When a designer wants to ensure he obtains the information he needs, he needs to specify explicitly the information to output before doing the actual circuit simulation. Only specified information is saved as result data. Accordingly, result data that is not saved cannot be displayed. To enable any result to be displayed without specifically selecting the data to output, it is necessary to perform a simulation that specifies all the circuit nodes to be output. As a result, the data of from all nodes need to be maintained. A large-scale circuit generates a large amount of data because all the results need to be saved. It is practically impossible to save all the data. Increasing the amount of data for result display also increases the retrieval time for result data and slows display speed. In addition, large-scale circuits increase simulation process time and therefore also increases the re-simulation time required when the circuit is partially modified or an element parameter is modified.
Concerning reduction of a storage area for saving simulation results, Japanese Unexamined Patent Publication No. Hei 11(1999)-96207 describes a technology of compressing the saved simulation result data. Japanese Unexamined Patent Publication NO. Hei 9(1997)-259151 discloses a technology that divides a circuit from an upstream and a downstream side of a signal path with respect to a modified circuit block and performs simulation for each part downstream of the modified block which would be affected by the modification of the block.
However, the technology described in Japanese Unexamined Patent Publication No. Hei 11(1999)-96207 additionally requires compression and decompression processes and further increases computation time due to the simulation and the result display. The technology described in Japanese Unexamined Patent Publication NO. Hei 9(1997)-259151 decreases the amount of memory used for computation, but does not decrease the storage capacity of auxiliary storage means for maintaining results. The circuit needs to be divided so as not to be dependent on the other simulation results and needs to be serially simulated. The process time is considered to increase.
The applicants made an application for patent (International Publication 03/036523 in the form of a brochure). The simulation method according to the application includes first and second processes. The first process performs simulation and saves a result so that a result output node corresponds to a higher hierarchical circuit node for hierarchical circuit data. The second process performs simulation under a specified initial condition for a lower hierarchical circuit node using the simulation result saved by the above-mentioned process as input/output information about a circuit area containing the lower hierarchical circuit node.